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cy8cmbr2010 capsense ? express? 10-button controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-74495 rev. *a revised august 16, 2012 10 button capsense? controller features easy to use capaciti ve button controller ? ten-button solution configurable through hardware straps ? no software tools or programming required ? ten general-purpose outputs (gpo) ? gpos linked to capsense buttons ? gpos support direct led drive smartsense? auto-tuning ? maintains optimal button performance even in noisy environ- ment ? capsense parameters dynamically set in runtime ? saves time and effort in device tuning ? wide parasitic capacitance (c p ) range (5 pf - 40 pf) noise immunity ? specifically designed for superi or noise immunity to external radiated and conducted noise ? low radiated noise emission system diagnostics of capsense buttons - reports faults at device power up ? button shorts ? improper value of modulator capacitor (c mod ) ? out of range c p value advanced features ? robust sensing even with closely spaced buttons - flanking sensor suppression (fss) ? user-configurable led effects ? on-system power-on ? led on time after button release ? supports analog voltage output (requires external resistors) ? serial debug data output ? simplifies production-line testing and system debug wide operating voltage range ? 1.71 v to 5.5 v ? ideal for both regulated and unregulated battery applications low power consumption ? average current consumption of 21 a [1] per button ? deep sleep current: 100 na industrial temperature range: ?40 c to +85 c 32-pin quad flat no leads (qfn) package (5 mm 5 mm 0.6 mm) overview the cy8cmbr2010 capsense express ? capacitive touch sensing controller saves time and money, quickly enabling a capacitive touch sensing user interface in your design. it is a hardware-configurable device and does not require any software tools, firmware coding, or device programming. this device is enabled with cypress?s revolutionary smartsense? auto-tuning algorithm. smartsense? auto-tuning ends the need to manually tune the user interface during development and production ramp. this speeds the time to volume and saves valuable engineering time, test time and production yield loss. the cy8cmbr2010 capsense controller supports up to ten capacitive touch sensing butt ons and ten general purpose outputs (gpo). the gpo is an active low output controlled directly by the capsense input making it ideal for a wide variety of consumer, industrial, and medical applications. the wide operating range of 1.71 v to 5.5 v enables unregulated battery operation, further saving component cost. the same device can also be used in different applications with varying power supplies. this device supports ultra low-power consumption in both run mode and deep sleep modes to stretch battery life. in addition, this device also supports many advanced features which enhance the robustness and user interface of the end solution. some of the key advanced features include noise immunity and fss. noise immunity improves the immunity of the device against radiated and conducted noise, such as audio and radio frequency (rf) noise. fss prov ides robust sensing even with closely spaced buttons. fss is a critical requirement in small form factor applications. power-on led effects provide a visual feedback to the design at power-on. this improves the aesthetic value of the end product. system diagnostics test for design faults at power-on and report any failures. this simplifies production line testing and reduces manufacturing costs. serial debug data output gives the critical information about the design, such as button c p and signal-to-noise ratio (snr). this further helps in production line testing. note 1. 21 a per button (4-buttons used, 3% touch time, 10 pf < cp of all buttons < 20 pf, button scan rate = 556 ms, with power con sumption optimized, noise immunity level ?normal?, cs0 sensitivity ?high?).
cy8cmbr2010 document number: 001-74495 rev. *a page 2 of 31 contents pinout ................................................................................ 3 typical circuits ................................................................. 4 configuring the cy8cmbr2010 6 . ............ .............. ........... device features ................................................................ 6 capsense buttons ...................................................... 6 smartsense? auto-tuning ........................................ 6 general-purpose outputs ...... ..................................... 6 toggle on/off ........................................................... 7 flanking sensor suppression (fss) ........................... 7 noise immunity ............................................................ 7 led on time .............................................................. 7 button auto reset ............... ........................................ 8 power-on led effects ................................................. 9 analog voltage support ............................................ 10 led backlighting ....................................................... 11 sensitivity control for cs0 button ............................. 11 debounce control for cs0 button ............................. 11 system diagnostics ................................................... 11 serial debug data ............... ...................................... 12 power consumption and operating modes ................. 16 low power sleep mode ............................................ 16 deep sleep mode ...................................................... 16 response time ........ .............. .............. .............. ....... 17 layout guidelines and best practices ......................... 18 capsense button shapes .......................................... 19 button layout design ................................................ 19 recommended via-hole placement .......................... 19 example pcb layout design with ten capsense buttons and ten gpos .................................................... 20 electrical specifications ................................................ 22 absolute maximum ratings ... .................................... 22 operating temperature ............................................. 22 dc electrical characteristics ..................................... 23 ac electrical specifications ....................................... 25 capsense specifications .......................................... 26 ordering information ...................................................... 26 ordering code definitions ..... .................................... 26 package information ...................................................... 27 thermal impedance .................................................. 27 solder reflow specifications ..................................... 27 package diagram ............................................................ 27 appendix ......................................................................... 28 acronyms ........................................................................ 30 document conventions ................................................. 30 units of measure ....................................................... 30 numeric naming .................... .................................... 30 document history page ................................................. 31 sales, solutions, and legal information ...................... 31 worldwide sales and design s upport ......... .............. 31 products .................................................................... 31 psoc solutions ......................................................... 31
cy8cmbr2010 document number: 001-74495 rev. *a page 3 of 31 pinout table 1. pin diagram and definitions ? cy8cmbr2010 pin label type [2] description if unused 1 cs1 ai capsense button input, controls gpo1 ground 2 cs0 ai capsense button input, controls gpo0 ground 3 gpo0 do gpo activated by cs0 leave open 4 gpo1 do gpo activated by cs1 leave open 5 gpo2 do gpo activated by cs2 leave open 6 gpo3 do gpo activated by cs3 leave open 7 gpo4 do gpo activated by cs4 leave open 8 backlighting do gpo controlled by cs0?cs9 when analog output voltage is enabled leave open 9 ledfading ai controls the power-on led effects and analog voltage output leave open 10 cs0sensitivi ty ai controls the sensitivity and debounce values of cs0 ground 11 delay ai controls the led on time and serial debug data out ground 12 v ss pground n/a 13 toggle/fss ai controls the enabling/disabling of toggle on/off and fss ground 14 arst/emc ai controls the bu tton auto reset period, enabling / disabling noise immunity technique ground 15 scanrate/sl eep di controls the button scan rate ground 16 gpo5 do gpo activated by cs5 leave open 17 xres di device reset, active high input, with internal pull down leave open 18 gpo6 do gpo activated by cs6 leave open 19 gpo7 do gpo activated by cs7 leave open 20 gpo8 do gpo activated by cs8 leave open 21 gpo9 do gpo activated by cs9 leave open 22 cs9 ai capsense button input, controls gpo9 ground 23 cs8 ai capsense button input, controls gpo8 ground 24 cs7 ai capsense button input, controls gpo7 ground 25 cs6 ai capsense button input, controls gpo6 ground 26 cs5 ai capsense button input, controls gpo5 ground 27 cs4 ai capsense button input, controls gpo4 ground 28 v dd p power n/a 29 cs3 ai capsense button input, controls gpo3 ground 30 cs2 ai capsense button input, controls gpo2 ground 31 c mod ai external modulator capacitor, recommended value 2.2 nf (10%) n/a 32 v ss pground n/a cy8cmbr2010 qfn ( top view ) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 cs 0 cs 1 cs 2 cs 3 cs 4 cs 5 cs 6 cs 7 cs 8 cs 9 gpo 0 gpo 1 gpo 2 gpo 4 gpo 5 gpo 6 gpo 7 gpo 8 gpo 9 cmod xres v ss backlighting le dfad ing cs0sensi tivity delay arst/emc toggle/fss scanrate/sleep v ss v dd gpo 3 note 2. ai ? analog input; di ? digital input; do ? digital output; p ? power
cy8cmbr2010 document number: 001-74495 rev. *a page 4 of 31 typical circuits schematic #1: ten buttons with ten gpos figure 1. cy8cmbr2010 schematic 1 in figure 1 , the device is configured in the following manner: cs0-cs9 pins: 560 ? to capsense buttons ? ten capsense buttons (cs0 - cs9) gpo0-gpo9 pins: led and 5 k ? to v dd ? capsense buttons drivi ng 10 leds (gpo0-gpo9) c mod pin: 2.2 nf to ground ? modulator capacitor xres pin: floating ? for external reset toggle/fss pin: 5.1 k ? to ground ? toggle on/off disabled ? flanking sensor suppression (fss) enabled arst/emc pin: 1.5 k ? to ground ? button auto reset enabled ? noise immunity level ?normal? ledfading pin: 1.5 k ? to ground ? analog voltage support disabled ? power-on led effects sequence 1 backlighting pin: floating ? no led backlighting output, as analog voltage support dis- abled delay pin: 1.8 k ? to ground ? led on time of 1000 ms ? serial debug data out disabled cs0sensitivity pin: v dd ? cs0 sensitivity ?low? ? cs0 debounce = 99 scanrate/sleep pin: 8.8 k ? to ground ? power consumption optimization ? user configured scan rate = 298 ms ?
cy8cmbr2010 document number: 001-74495 rev. *a page 5 of 31 schematic #2: eight buttons with analog voltage output figure 2. cy8cmbr2010 schematic 2 in figure 2 , the device is configured in the following manner: cs0 - cs7 pins: 560 ? to capsense buttons; cs8, cs9 pins: ground ? eight capsense buttons (cs0 - cs7) ? cs8, cs9 buttons not used in design gpo0-gpo9 pins: connect to external resistive network ? eight gpos (gpo0 - gpo7) used for analog voltage output ? gpo8, gpo9 not used in design c mod pin: 2.2 nf to ground ? modulator capacitor xres pin: floating ? for external reset toggle/fss pin: v dd ? toggle on/off enabled ? flanking sensor suppression (fss) enabled arst/emc pin: v dd ? button auto reset enabled ? noise immunity level ?high? ledfading pin: ground ? analog voltage support enabled ? power-on led effects disabled backlighting pin: led and 5 k ? to v dd ? led backlighting output, as analog voltage support enabled delay pin: ground ? led on time disabled ? serial debug data out disabled cs0sensitivity pin: v dd ? cs0 sensitivity ?low? ? cs0 debounce = 99 scanrate/sleep pin: 8.3 k ? to ground ? power consumption optimization ? user configured scan rate = 210 ms ?
cy8cmbr2010 document number: 001-74495 rev. *a page 6 of 31 configuring th e cy8cmbr2010 the cy8cmbr2010 device features are configured using external resistors. the resistors on the hardware configurable pins are determined by the device upon power-on. the appendix on page 28 gives the matrix of features enabled using different external resistor configurations. to know more about the required settings for your design, refer to the cy8cmbr2010 design guide . device features capsense buttons supports up to ten capsense buttons. ground the csx pin to disable capsense button input. a 2.2 nf (10%) capacitor must be connected on the c mod pin for proper capsense operation. for proper capsense operation, ensure c p of each button is less than 40 pf. smartsense? auto-tuning supports auto-tuning of capsense parameters no manual tuning required; all parameters are automatically tuned by the device. reduces the design cycle time. ? no manual tuning. ensures portability of the user interface design. compensates printed circuit board (pcb) variations, device process variations, and pcb vendor changes. general-purpose outputs gpox pin outputs are strong drive [3] the gpox is controlled by the corresponding csx active low output ? supports sinking configuration for leds (see figure 3 ) if csx is disabled (grounded), then the corresponding gpox must be left floating a 5-ms pulse is sent after 350 ms (if noise immunity level is ?normal?) / 1000 ms (if noise im munity level is ?high?) after power-up on the gpox if the cs x fails the system diagnostics figure 3. example of gpo0 driven by cs0 cs0 gpo0 sensor ? touched sensor ? released button button table 2. advanced features supported by cy8cmbr2010 feature benefit toggle on/off button retains state on touch (on/off) flanking sensor suppression (fss) helps in distinguishing closely spaced buttons noise immunity improves device immunity to external noise (such as rf noise) led on time gives an led effect on button release button auto reset disables false output trigger, due to conducting object placed close to button power-on led effects provides visual effects to design at power-on analog voltage support external resistors can be used with gpos to generate analog voltage output led backlighting common gpo available for led drive if analog voltage support enabled sensitivity control for cs0 button and debounce control for cs0 button useful for special function buttons such as power button system diagnostics support for production testing and debugging serial debug data support for production testing and validating design low power sleep mode and deep sleep mode low power consumption note 3. when a pin is in strong drive mode, it is pulled up to v dd when the output is high and pulled down to ground when the output is low.
cy8cmbr2010 document number: 001-74495 rev. *a page 7 of 31 toggle on/off toggles the gpo state at each button touch (see figure 4 ). used for mechanical button replacement. for example, wall switch. flanking sensor suppression (fss) helps in distinguishing closely spaced buttons. also used in situations with buttons having opposite functions. for example, an interface with two buttons for brightness control (up or down). fss action can be explained for following different scenarios: 1. when only one button is touche d, it is reported as on. see figure 5 . 2. when more than one button is detected as on and previously one of those buttons was touched, then the previously touched button is reported as on. see figure 6 . noise immunity improves the immunity of the device against external radiated and conducted noise. reduces the radiated noise emission. possible noise immunity levels are ?normal? and ?high?. led on time provides better visual feedba ck when a button is released and improves the design?s aesthetic value. the gpox is driven low for a specified interval after the corresponding csx button is released (see figure 7 ). when a button gets reset (refer to button auto reset on page 8 ), led on time is not applied on the corresponding gpo. applicable to the gpo of the last button released. in figure 8 on page 8 , gpo0 goes high prematurely (prior to led on time expiration) because cs1 button is released. therefore, the led on time counter is reset. now, gpo1 remains low for led on ti me after releasing cs1. led on time can range from 0?2000 ms. led on time resolution is 20 ms. figure 4. example of togg le on/off feature on gpo0 figure 5. fss when only one button is touched figure 6. fss when multiple buttons are touched with one button on previously cs0 gpo0 no button is on prior to the touch cs1 is reported as on upon touch cs1 is touched, reported on cs2 also touc hed alongwith cs1; only cs1 is reported on
cy8cmbr2010 document number: 001-74495 rev. *a page 8 of 31 figure 7. example led on timing diagram on gpo0 figure 8. example led on timing diagram on gpo0 and gpo1 button auto reset prevents button stuck, due to metal object placed close to button. useful when gpo output to be kept on only for a specific time. if enabled, the gpox is driv en for a maximum of arst time when csx is continuously touched. see figure 9 . auto reset period is 20 s. figure 9. example of button auto reset on gpo0 cs0 gpo0 start ? led ? on ? time ? counter reset ? led ? on ? time ? counter led ? on ? time cs0 gpo0 cs1 gpo1 start ? led ? on ? time ? counter restart ? led ? on ? time ? counter reset ? led ? on ? time ? counter led ? on ? time cs0 gpo0 auto ? reset ? period gpo0 ? is ? not ? driven ? after ? auto ? reset ? period button ? is ? touched ? for ? more ? than ? the ? auto ? reset ? period
cy8cmbr2010 document number: 001-74495 rev. *a page 9 of 31 power-on led effects provides a visual effect at device power up. after power on, all the leds show dimming and fading effects for an initial time. seen on gpox when csx is enabled. all capsense buttons are disabled during this time. if any capsense button, csx fa ils the power-on self test then these effects are not seen on the corresponding gpox. to know more about power-on self test, refer system diagnostics . the following parameters are set for led effects: ? low brightness ? minimum intensity of led brightness. ? low brightness time ? time for which the led stays in the low brightness state. ? ramp up time ? time taken by the led to go from low brightness state to high brightness state. ? high brightness ? maximum intensity of led brightness. ? high brightness time ? time for which the led stays in the high brightness state. ? ramp down time ? time taken by the led to go from high brightness state to low brightness state. ? repeat rate ? the number of times the effect cycle is repeated. the effects are seen after the device initialization time from power-on. this time is less than 350 ms (if noise immunity level is ?normal?) and less than 1000 ms (if noise immunity level is ?high?). the device responds to any button touch only after the effects are complete. there are three different predefined power-on led effects available. the different effects are as follows ? ? all the leds concurrently go to high brightness state and come back to low brightness state. see figure 10 . ? all the leds concurrently go to high brightness state and come back to low brightness state. this is repeated once (repeat rate = 2). see figure 11 . ? all the leds sequentially go to high brightness state and come back to low brightness state. see figure 12 on page 10 . figure 10. power-on led effect sequence 1 figure 11. power-on led effect sequence 2 led ? brightness 100% 0% 1000 ? ms 400 ? ms 1000 ? ms 400 ? ms power ? on 350 ? ms/ 1000 ? ms normal ? operation effects ? completed 0% ra m p ? u p ra m p ? d o w n 3150 ? ms ? / ? 3800 ? ms led ? brightness 100% r a m p ? u p r a m p ? d o w n 0% 500 ? ms 200 ? ms 500 ? ms 200 ? ms power ? on 350 ? ms/ 1000 ? ms 100% r a m p ? d o w n 0% 500 ? ms 200 ? ms 500 ? ms 200 ? ms r a m p ? u p normal ? operation effects ? completed 0% 3150 ? ms ? / ? 3800 ? ms
cy8cmbr2010 document number: 001-74495 rev. *a page 10 of 31 figure 12. power-on led effect sequence 3 with two button design analog voltage support a general external resistive network with a host processor is shown in figure 13 . host can be configured to perf orm different functions based on the voltage level at input pins. this is controlled by switches. these switches can be controlled by capsense buttons. if enabled, gpos replace these switches in the network. gpos are in open drain low drive mode. gpos cannot be used for the resistive network and led drive simultaneously. instead, the backlighting pin acts as a gpo for led drive, controlled by all the csx buttons. if only one button needs to be on for analog voltage support, fss should be enabled. for cy8cmbr2010, a simple external resistive network is shown in figure 14 . figure 13. a general external resistive network figure 14. analog voltage support for cy8cmbr2010 gpo0 ? led ? brightness r a m p ? u p r a m p ? d o w n 300 ? ms 300 ? ms power ? on 350ms/ 1000 ? ms normal ? operation effects ? completed r a m p ? d o w n r a m p ? u p gpo1 ? led ? brightness 300 ? ms 300 ? ms 1550 ? ms ? / ? 2200 ? ms 0% 0% 0% 100% 100% host ? processor v dd v dd r 1 r 2 r 3 r 4 r 7 r 6 r 8 r 5 key ? 1 key ? 2 host ? processor v dd v dd r 1 r 2 r 3 r 4 r 7 r 6 r 8 r 5 key ? 1 key ? 2 gpo2 gpo1 gpo3 gpo4 gpo6 gpo5 gpo7 gpo8
cy8cmbr2010 document number: 001-74495 rev. *a page 11 of 31 led backlighting acts as a gpo for led drive; controlled by all the capsense buttons csx. can be used when analog voltage support is enabled. backlighting is a strong drive, active low output. it goes low if one or more capsense button is touched. sensitivity control for cs0 button sensitivity of all buttons except cs0 is ?high?. cs0 can have ?low? sensitivity as well for special purpose, such as a power button. use higher sensitivit y setting when the overlay thickness is higher. debounce control for cs0 button avoids false triggering of button due to noise spike or any other glitches in the system. specifies the minimum time for which cs0 has to be touched, for an output trigger. useful for added func tionalities. example, linking system reset to touch time corresponding to cs0 debounce. system diagnostics a built-in power-on self test (post) mechanism performs some tests at power-on reset (por), which can be useful in production testing. if any button fails these tests, a 5 ms pulse is sent out on the corresponding gpo within 350 ms (if noise immunity level is ?normal?) / 1000 ms (if noise immunity level is ?high?) after por. following tests are performed on all the buttons ? button shorted to ground if any button is found to be shorted to ground, it is disabled. see figure 15 . figure 15. button shorted to ground button shorted to v dd if any button is found to be shorted to v dd , it is disabled. see figure 16 . figure 16. button shorted to v dd button to button short if two or more buttons are found to be shorted to each other, all of these buttons are disabled. see figure 17 . figure 17. button to button short cy8cmbr2010 sensor shorting button cy8cmbr2010 sensor shorting v dd button cy8cmbr2010 sensor shorting sensor button button
cy8cmbr2010 document number: 001-74495 rev. *a page 12 of 31 improper value of c mod recommended value of c mod is 2 nf to 2.4 nf. if the value of c mod is found to be less than 1 nf or greater than 4 nf, all the buttons are disabled. button c p > 40 pf if the parasitic capacitance (c p ) of any button is found to be more than 40 pf, that button is disabled. figure 18. example showing cs0 and cs1 passing the post and cs2 and cs3 failing in figure 18 , cs0 and cs1 buttons are enabled; cs2 and cs3 buttons are disabled because they failed the power-on self test. a 5 ms pulse is observed on gpo2 and gpo3. serial debug data used to see capsense data through the delay pin. if enabled, debug data is transmitted on delay pin using uart communication protocol. serial data is sent out with ~115,200 baud rate. the cypress multichart tool can be used to view the data as a graph. the following data is sent out by the device for all the buttons enabled ? ? firmware revision ? capsense button status ? gpo status ? raw counts of all buttons ? baseline of all buttons ? difference counts of all buttons ? parasitic capacitance of all buttons ? snr of all buttons ? system diagnostics data ? compensated idac value for more information on raw count, baseline, difference count, parasitic capacitanc e and snr, refer getting started with capsense section 2. for more information on multichart tool, refer an2397 capsense data viewing tools method 2. the multichart tool arranges the data in the format as shown in table 3 the serial debug data is sent by the device in the order as per table 4 . 5ms ? pulse gpo3 gpo2 gpo1 (high) gpo0 (high) 5ms ? pulse table 3. serial debug data arranged in multichart # raw count array baseline array signal array msb lsb msb lsb msb lsb 0 0x80 fw revision 0x00 cs_status_msb idac_comp gpo_status_msb 1 cs0_cp cs1_cp 0x00 cs_status_lsb 0x00 gpo_status_lsb 2 cs0_rawcount cs0_baseline cs0_diffcount 3 cs1_rawcount cs1_baseline cs1_diffcount 4 cs2_rawcount cs2_baseline cs2_diffcount 5 cs3_rawcount cs3_baseline cs3_diffcount 6 cs4_rawcount cs4_baseline cs4_diffcount 7 cs5_rawcount cs5_baseline cs5_diffcount 8 cs6_rawcount cs6_baseline cs6_diffcount 9 cs7_rawcount cs7_baseline cs7_diffcount 10 cs8_rawcount cs8_baseline cs8_diffcount 11 cs9_rawcount cs9_baseline cs9_diffcount 12 cs2_cp cs3_cp cs4_cp cs5_cp cs7_cp cs8_cp 13 0x00 cs0_cs1_snr cs6_cp cs4_cs5_snr cs9_cp cs8_cs9_snr 14 0x00 cs2_cs3_snr 0x00 cs 6_cs7_snr 0x00 cmod_mask
cy8cmbr2010 document number: 001-74495 rev. *a page 13 of 31 15 vdd_short_mask gnd_short_mask pin_to_pin_short_mask 16 0x00 0x01 0x00 0x02 cp_high_mask table 3. serial debug data arranged in multichart (continued) # raw count array baseline array signal array msb lsb msb lsb msb lsb table 4. serial debug data output sent by cy8cmbr2010 byte data notes 0 0x0d dummy data for multi chart 1 0x0a 20x80 ? 3 fw revision firmware revision 4 cs0_cp cs0 parasitic capacitance (pf) in hex 5 cs1_cp cs1 parasitic capacitance (pf) in hex 6 cs0_rawcount_msb unsigned 16-bit integer 7 cs0_rawcount_lsb 8 cs1_rawcount_msb unsigned 16-bit integer 9 cs1_rawcount_lsb . . . . . . 24 cs9_rawcount_msb unsigned 16-bit integer 25 cs9_rawcount_lsb 26 cs2_cp cs2 parasitic capacitance (pf) in hex 27 cs3_cp cs3 parasitic capacitance (pf) in hex 28 0x00 ? 29 cs0_cs1_snr cs0 and cs1 snr 30 0x00 ? 31 cs2_cs3_snr cs2 and cs3 snr 32 vdd_short_mask_msb system diagnostics data for cs pins shorted to v dd 33 vdd_short_mask_lsb 34 0x00 ? 35 0x01 36 0x00 ? 37 cs_status_msb gives cs status for cs8?cs9 38 0x00 ? 39 cs_status_lsb gives cs status for cs0?cs7 40 cs0_baseline_msb unsigned 16-bit integer 41 cs0_baseline_lsb 42 cs1_baseline_msb unsigned 16-bit integer 43 cs1_baseline_lsb . . . . . . 58 cs9_baseline_msb unsigned 16-bit integer 59 cs9_baseline_lsb
cy8cmbr2010 document number: 001-74495 rev. *a page 14 of 31 system diagnostics data contains the post results. this is as follows: vdd_short_mask ? this contains the info rmation about any button short to v dd . the msb and lsb of this data contain the following. 60 cs4_cp cs4 parasitic capacitance (pf) in hex 61 cs5_cp cs5 parasitic capacitance (pf) in hex 62 cs6_cp cs6 parasitic capacitance (pf) in hex 63 cs4_cs5_snr cs4 and cs5 snr 64 0x00 ? 65 cs6_cs7_snr cs6 and cs7 snr 66 gnd_short_mask_msb system diagnostics data for cs pins shorted to gnd 67 gnd_short_mask_lsb 68 0x00 ? 69 0x02 70 idac_comp compensated idac 71 gpo_status_mask_msb gives gpo status for gpo8?gpo9 72 0x00 ? 73 gpo_status_mask_lsb gives gpo status for gpo0?gpo7 74 cs0_diffcount_msb unsigned 16-bit integer 75 cs0_diffcount_lsb 76 cs1_diffcount_msb unsigned 16-bit integer 77 cs1_diffcount_lsb . . . . . . 92 cs9_diffcount_msb unsigned 16-bit integer 93 cs9_diffcount_lsb 94 cs7_cp cs7 parasitic capacitance (pf) in hex 95 cs8_cp cs8 parasitic capacitance (pf) in hex 96 cs9_cp cs9 parasitic capacitance (pf) in hex 97 cs8_cs9_snr cs8 and cs9 snr 98 0x00 ? 99 cmod_mask system diagnostics data for c mod out of range 100 pin_to_pin_shorted_mask_msb system diagnostics data for cs pin to pin short 101 pin_to_pin_shorted_mask_lsb 102 cp_high_mask_msb system diagnositcs data for cs button cp > 40 pf 103 cp_high_mask_lsb 104 0x00 dummy data for multichart 105 0xff 106 0xff table 4. serial debug data output sent by cy8cmbr2010 (continued) byte data notes
cy8cmbr2010 document number: 001-74495 rev. *a page 15 of 31 for csx, the corresponding bit is written as: 0 ...........................................if the csx is not shorted to v dd 1 .................................................if the csx is shorted to v dd gnd_short_mask ? this contains the inform ation about any button short to ground. th e msb and lsb of this data contain the following. for csx, the corresponding bit is written as: 0 ...................................... if the csx is not shorted to ground 1 ............................................ if the csx is shorted to ground cmod_mask ? this contains the information about the c mod value within range. this byte is written as: 0 ...... if the c mod value is within range (between 1 nf?4 nf) 1 ..................................................... if the c mod value > 4 nf 2 ..................................................... if the c mod value < 1 nf pin_to_pin_short_mask ? this contains the information about any button to button short. the msb and lsb of this data contain the following. for csx, the corresponding bit is written as: 0................if the csx pin is no t shorted to any other csy pin 1........................ if the csx pin is shorted to another csy pin cp_high_mask ? this contains the information about the csx button c p value within range. the msb and lsb of this data contain the following for csx, the corresponding bit is written as: 0................................................. if the csx c p value < 40 pf 1................................................. if the csx c p value > 40 pf table 5. vdd_short_mask name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vdd_short_mask_lsb cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 vdd_short_mask_msb cs9 cs8 table 6. gnd_short_mask name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gnd_short_mask_lsb cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 gnd_short_mask_msb cs9 cs8 table 7. pin_to_pin_short_mask name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pin_to_pin_short_mask_lsb cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 pin_to_pin_short_mask_msb cs9 cs8 table 8. cp_high_mask name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cp_high_mask_lsb cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 cp_high_mask_msb cs9 cs8
cy8cmbr2010 document number: 001-74495 rev. *a page 16 of 31 power consumption and operating modes the cy8cmbr2010 is designed to meet the low power requirements of battery powered applications. to design for the lowest operating current ? ground all unused capsense inputs minimize cp using the design guidelines in getting started with capsense , section 3.7.1 lower the supply voltage (val id range: 1.71 v to 5.5 v) reduce sensitivity of cs0 button configure design to be po wer consumption optimized use ?high? noise immunity level only if required use a higher button scan rate or deep sleep operating mode to know more about the steps to reduce power consumption, refer to the cy8cmbr2010 design guide section 5. low power sleep mode the following flow chart describes the low power sleep mode operation. figure 19. low power sleep mode operation the button scan rate is equal to the sum of the time the device scans and sleeps. an external resistor defin es button scan rate offset. the offset is added to a consta nt to get the button scan rate. to know about the button scan rate offset and the button scan rate constant, refer to table 22 on page 29 and table 23 on page 30 in appendix . the range of scan rate is 25 to 556 ms. deep sleep mode figure 20. scanrate/sleep pin connection to enable deep sleep mode scan all buttons with button scan rate constant no button touched for 15 secs? yes scan all buttons with user defined button scan rate is any button active? yes no no scan all buttons with external reistor r (controls scan rate)
cy8cmbr2010 document number: 001-74495 rev. *a page 17 of 31 to enable the deep sleep mode, the scanrate/sleep pin should be connected to host controller as shown in figure 20 on page 16 . host controller should pull the pin to v dd for the device to go into deep sleep. in deep sleep mode, all blocks are turned off and the device power consumption is approximately 0.1 a. there is no capsense scanning in deep sleep mode. scanrate/sleep pin should be pulled low for the device to wake up from deep sleep. when device comes out of deep sleep mode, the capsense system is reinitialized. typical time for reinitialization is 20 ms (if noise immunity leve l is ?normal?) or 50 ms (if noise immunity level is ?high?). any button touch within this time is not reported. at power on, the scanrate/sleep pin should be pulled low. if the scanrate/sleep pin is pulled high at power on, then the device goes to deep sleep after the post and power-on led effects are completed. response time response time is the minimum amount of ti me the button should be touched for the de vice to detect as valid button touch. it is given by following equation where rt fbt is response time for first button touch rt cbt is response time for consecutive button touch after first button touch debounce for cs1?cs9 = 3 debounce for cs0 can be one of 3 / 24 / 48 / 99 round down is the greatest integer less than or equal to ((debounce ? 1)/3) for example, consider an eight button design with the delay pin connected to ground through a 3.2 k ? resistor. this results in a response time optimized design with a user def ined button scan rate of 556 ms (as per table 22 on page 29 and table 23 on page 30 ). assuming that cs0 is not used in the desi gn, the debounce value for each button (cs1?cs8) is 3. the button scan rate constant for such a design is 50 ms (as per table 23 on page 30 ). the response time for such a design is given as ?
cy8cmbr2010 document number: 001-74495 rev. *a page 18 of 31 layout guidelines and best practices table 9. layout guidelines and best practices sl. no. category min max recommendations/remarks 1 button shape ? ? solid round pattern, round with led hole, rectangle with round corners 2 button size 5 mm 15 mm refer design toolbox . 3 button-button spacing equal to button ground clearance ? 8 mm (y dimension in figure 22 on page 19 ) 4 button ground clearance 0.5 mm 2 mm refer design toolbox (x dimension in figure 22 on page 19 ). 5 ground flood ? top layer ? ? hatched ground 7 mil trace and 45 mil grid (15% filling). 6 ground flood ? bottom layer ? ? hatched ground 7 mil trace and 70 mil grid (10% filling). 7 trace length from button pad to capsense controller pins ? 450 mm refer design toolbox . 8 trace width 0.17 mm 0.20 mm 0.17 mm (7 mil) 9 trace routing ? ? traces should be routed on the non button side. if any non capsense trace crosses capsense trace, ensure that intersection is orthogonal. 10 via position for the buttons ? ? via should be placed near the edge of the button pad to reduce trace length thereby increasing sensitivity. 11 via hole size for button traces ? ? 10 mil 12 no. of via on button trace 1 2 1 13 distance of capsense series resistor from button pin ? 10 mm place capsense series resistors close to the device for noise suppression.capsense resistors have highest priority; place them first. 14 distance between any capsense trace to ground flood 10 mil 20 mil 20 mil 15 device placement ? ? mount the device on the layer opposite to button. the capsense trace length between the device and buttons should be minimum (see trace length above) 16 placement of components in two layer pcb ? ? top layer ? buttons bottom layer ? device, other components and traces. 17 placement of components in four layer pcb ? ? top layer ? buttons second layer ? capsense traces and v dd (avoid v dd traces below the buttons) third layer ? hatched ground bottom layer ? capsense controller, other components and non capsense traces 18 overlay thickness 0 mm 5 mm refer design toolbox . 19 overlay material ? ? should be non-condu ctive material. gla ss, abs plastic, formica, wood and so on. there should be no air gap between pcb and overlay. use adhesive to stick the pcb and overlay. 20 overlay adhesives ? ? adhesive should be non conductive and dielectrically homogenous. 467mp and 468mp adhesives made by 3m are recommended. 21 led back lighting ? ? cut a hole in the button pad and use rear mountable leds. refer to the pcb layout below. 22 board thickness ? ? standard board thickness for capsense fr4 based designs is 1.6 mm.
cy8cmbr2010 document number: 001-74495 rev. *a page 19 of 31 capsense button shapes figure 21. capsense button shapes button layout design figure 22. button layout design x: button to ground clearance (refer to layout guidelines and best practices on page 18 ). y: button to button clearance (refer to layout guidelines and best practices on page 18 ). recommended via-hole placement figure 23. recommended via-hole placement ?
cy8cmbr2010 document number: 001-74495 rev. *a page 20 of 31 example pcb layout design with ten capsense buttons and ten gpos figure 24. top layer ? capsense ? csx ?? leds ?
cy8cmbr2010 document number: 001-74495 rev. *a page 21 of 31 figure 25. bottom layer ? v dd ? trace ? capsense ? traces ? gnd ? ? led ? traces ? hardware ? strap ? resistors ? led ? resistors ? cy8cmbr2010
cy8cmbr2010 document number: 001-74495 rev. *a page 22 of 31 electrical specifications this section presents the dc and ac electric al specifications of the cy8cmbr2010 device. absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. operating temperature table 10. absolute maximum ratings parameter description min typ max unit conditions t stg storage temperature ?55 +25 +125 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage at temperatures above 85 c degrades reliability. v dd supply voltage relative to v ss ?0.5 ? +6.0 v v io dc voltage on capsense inputs and digital output pins v ss ? 0.5 ? v dd + 0.5 v i mig maximum current into any gpo pin ?25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd lu latch up current ? ? 200 ma in accordance with jesd78 standard table 11. operating temperature parameter description min typ max unit notes t a ambient temperature ?40 ? +85 c t c commercial temperature 0 ? +70 c t j operational die temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. refer to table 19 on page 27 . the user must limit the power consumption to comply with this requirement.
cy8cmbr2010 document number: 001-74495 rev. *a page 23 of 31 dc electrical characteristics dc chip level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 12. dc chip-level specifications parameter description min typ max unit notes v dd [4, 5, 6] supply voltage 1.71 ? 5.5 v i dd supply current ? 3.4 4.0 ma v dd = 3.0 v, t a = 25 c i da active current ? 3.4 4.0 ma v dd = 3.0 v, t a = 25 c, continuous button scan i dl low power sleep current ? 1.07 1.50 av dd = 3.0 v, t a = 25 c i ds deep sleep current ? 0.1 1.05 av dd = 3.0 v, t a = 25 c i av1 average current ? 85.90 ? a 4-buttons used, 3% touch time, 10 pf < c p of all buttons < 20 pf, button scan rate = 556 ms, with power consumption optimized, noise immunity level ?normal?, cs0 sensitivity ?high? i av2 average current ? 131.50 ? a 8-buttons used, 5% touch time, 10 pf < c p of all buttons < 20 pf, button scan rate = 556 ms, with response time optimized, noise immunity level ?normal?, cs0 sensitivity ?high? i av3 average current ? 168.10 ? a 10-buttons used, 5% touch time, 10 pf < cp of all buttons < 20 pf, button scan rate = 419 ms, with response time optimized, noise immunity level ?normal?, cs0 sensitivity ?high? notes 4. when v dd remains in the range from 1.75 v to 1.9 v for more than 50 s, the slew rate when moving from the 1.75 v to 1.9 v range to greater than 2 v must be slower than 1 v/500 s. this helps to avoid triggering por. t he only other restriction on slew rates for any other voltage rang e or transition is the srpower_up parameter. 5. after power-down, ensure that v dd falls below 100 mv before powering back up. 6. for proper capsense block functionality, if the drop in v dd exceeds 5% of the base v dd , the rate at which v dd drops should not exceed 200 mv/s. base v dd can be between 1.8 v and 5.5 v.
cy8cmbr2010 document number: 001-74495 rev. *a page 24 of 31 dc general-purpose i/o specifications these tables list guaranteed maximum and mi nimum specifications for the voltage a nd temperature ranges : 3.0 v to 5.5 v and ?40 c t a 85 c, 2.4 v to 3.0 v and ?40 c t a 85 c, and 1.71 v to 2.4 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. . table 13. 3.0 v to 5.5 v dc general-purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.20 ? ? v i oh 10 a, maximum of 10 ma source current in all i/os v oh2 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.90 ? ? v i oh = 1 ma, maximum of 20 ma source current in all i/os v oh3 high output voltage on gpo5, backlighting, delay pins v dd ? 0.20 ? ? v i oh < 10 a, maximum of 10 ma source current in all i/os v oh4 high output voltage on gpo5, backlighting, delay pins v dd ? 0.90 ? ? v i oh = 5 ma, maximum of 20 ma source current in all i/os v ol low output voltage on all gpos, backlighting, delay pins ? ? 0.75 v i ol = 25 ma, v dd > 3.3 v, maximum of 60 ma sink current on gpo0, gpo1, gpo2, gpo3, gpo4, backlighting, delay pins and 60 ma sink current on gpo5, gpo6, gpo7, gpo8, gpo9 pins. v il input low voltage ? ? 0.80 v v ih input high voltage 2.00 ? ? v table 14. 2.4 v to 3.0 v dc general-purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.20 ? ? v i oh < 10 a, maximum of 10 ma source current in all i/os v oh2 high output voltage on gpo0?gpo9 (except gpo 5) v dd ? 0.40 ? ? v i oh = 0.2 ma, maximum of 10 ma source current in all i/os v oh3 high output voltage on gpo5, backlighting, delay pins v dd ? 0.20 ? ? v i oh < 10 a, maximum of 10 ma source current in all i/os v oh4 high output voltage on gpo5, backlighting, delay pins v dd ? 0.50 ? ? v i oh = 2 ma, maximum of 10 ma source current in all i/os v ol low output voltage on all gpos, backlighting, delay pins ? ? 0.75 ? i ol = 5 ma, maximum of 30 ma sink current on gpo0, gpo1, gpo2, gpo3, gpo4, backlighting, delay pins and 30 ma sink current on gpo5, gpo6, gpo7, gpo8, gpo9 pins. v il input low voltage ? ? 0.72 v v ih input high voltage 1.40 ? ? v table 15. 1.71 v to 2.4 v dc general-purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.20 ? ? v i oh = 10 a, maximum of 10 ma source current in all i/os v oh2 high output voltage on gpo0?gpo9 (except gpo5) v dd ? 0.50 ? ? v i oh = 0.5 ma, maximum of 10 ma source current in all i/os
cy8cmbr2010 document number: 001-74495 rev. *a page 25 of 31 ac electrical specifications ac chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac general-purpose i/o specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. v oh3 high output voltage on gpo5, backlighting, delay pins v dd ? 0.20 ? ? v i oh = 100 a, maximum of 10 ma source current in all i/os v oh4 high output voltage on gpo5, backlighting, delay pins v dd ? 0.50 ? ? v i oh = 2 ma, maximum of 10 ma source current in all i/os v ol low output voltage on all gpos, backlighting, delay pins ??0.4?i ol = 5 ma, maximum of 20 ma sink current on gpo5, gpo6, gpo7, gpo8, gpo9 pins and 30 ma sink current on gpo0, gpo1, gpo2, gpo3, gpo4 , backlighting, delay pins. v il input low voltage ? ? 0.3 v dd v v ih input high voltage 0.65 v dd ??v table 15. 1.71 v to 2.4 v dc general-purpose i/o specifications (continued) parameter description min typ max unit notes table 16. ac chip ? level specifications parameter description min max unit notes sr power_up power supply slew rate ? 250 v/ms v dd slew rate during power-up. t xrst external reset pulse width at power-up 1 ? ms applicable after device power supply is active t xrst2 external reset pulse width after power-up 10 ? s applicable after device v dd has reached max value table 17. ac general-purpose i/o specifications parameter description min typ max unit notes t rise1 rise time, strong mode on gpo0?gpo9 (except gpo5), c load = 50 pf 15?80nsv dd = 3.0 to 3.6 v, 10% to 90% t rise2 rise time, strong mode low supply on gpo5, backlighting, delay pins, c load = 50 pf 10?50nsv dd = 3.0 to 3.6 v, 10% to 90% t rise3 rise time on gpo0?gpo9 (except gpo5), c load = 50 pf 15?80nsv dd = 1.71 to 3.0 v, 10% to 90% t rise2 rise time, strong mode low supply on gpo5, backlighting, delay pins, c load = 50 pf 10?80nsv dd = 1.71 to 3.0 v, 10% to 90% t fall1 fall time, strong mode on all gpos, backlighting, delay pins, c load = 50 pf 10?50nsv dd = 3.0 to 3.6 v, 90% to 10% t fall2 fall time, strong mode low supply on all gpos, backlighting, delay pins, c load = 50 pf 10?70nsv dd = 1.71 to 3.0 v, 90% to 10%
cy8cmbr2010 document number: 001-74495 rev. *a page 26 of 31 capsense specifications ordering information ordering code definitions table 18. capsense specifications parameter description min typ max unit notes c p parasitic capacitance 5 ? (c p + c f ) < 40 [7] pf c p is the total capacitance seen by the pin when no finger is present. c p is sum of c button , c trace , and capacitance of the vias and c pin . c f finger capacitance 0.25 ? (c p + c f ) < 40 [7] pf c f is the capacitance added by the finger touch. c pin capacitive load on pins as input 0.5 1.7 7 pf c mod external modulator capacitor 2 2.2 2.4 nf mandatory requirement r s series resistor between pin and the button ? 560 616 ? reduces the rf noise. note 7. the max value of parasitic capacitance is 40 pf when the temperature is above 0 c, and 38 pf at ?45 c. ordering code package type operating temperature capsense inputs gpo?s xrespin CY8CMBR2010-24LQXI 32-pin (5 5 0.6 mm) qfn industrial 10 10 yes CY8CMBR2010-24LQXIt 32-pi n (5 5 0.6 mm) qfn (tape and reel) industrial 10 10 yes x = blank or t blank = tube; t = tape and reel temperature range: i = industrial = ?40 c to 85 c pb-free package type: lq = 32-pin qfn speed: 24 mhz part number mechanical button replacement technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress c cy mbr 2010 - 24 lq 8 x x i
cy8cmbr2010 document number: 001-74495 rev. *a page 27 of 31 package information thermal impedance solder reflow specifications ta b l e 2 0 shows the solder reflow temperature limits that must not be exceeded. package diagram figure 26. 32-pin qfn (5 5 0.55 mm) lq32 3.5 3.5 e-pad (sawn) package outline, 001-42168 table 19. thermal impedances per package package typical ja [8] 32-pin qfn [9] 20 c/w table 20. solder reflow specifications package minimum peak temperature (t c ) maximum time above t c ? 5 c 32-pin qfn 260 ? c 30 seconds 001-42168 *d notes 8. t j = t a + power ? ja . 9. to achieve the thermal impedance specified for the qfn package, the center thermal pad must be soldered to the pcb ground pla ne.
cy8cmbr2010 document number: 001-74495 rev. *a page 28 of 31 appendix table 21. device features vs. resistor configuration matrix features comments pin configuration device pin name toggle on/off / flanking sensor suppression (fss) toggle on/off flanking sensor suppression (fss) to g g l e / f s s disabled disabled ground / floating enabled disabled 1.5 k ? (5%) to ground disabled enabled 5.1 k ? (5%) to ground enabled enabled v dd noise immunity / button auto reset noise immunity button auto reset arst/emc normal disabled ground / floating normal enabled 1.5 k ? (5%) to ground high disabled 5.1 k ? (5%) to ground high enabled v dd led on time / serial debug data led on time (ms) serial debug data delay 0 disabled ground / 300 ? (1%) to ground 20 330 ? (1%) to ground 40 360 ? (1%) to ground ???? ???? 1980 3270 ? (1%) to ground 2000 3300 ? (1%) to ground 0 enabled 7000 ? (1%) to ground 20 7030 ? (1%) to ground 40 7060 ? (1%) to ground ???? ???? 1980 9970 ? (1%) to ground 2000 10000 ? (1%) to ground power-on led effects / analog voltage support / led backlighting power-on led effects analog voltage support / led backlighting ledfading disabled enabled ground led effect 1 disabled 1.5 k ? (5%) to ground led effect 2 disabled 5.1 k ? (5%) to ground led effect 3 disabled v dd disabled disabled floating sensitivity and debounce control for cs0 button sensitivity control for cs0 button debounce control for cs0 button cs0sensitivity high 3 ground / floating high 24 1.5 k ? (5%) to ground high 48 5.1 k ? (5%) to ground low 99 v dd
cy8cmbr2010 document number: 001-74495 rev. *a page 29 of 31 table 22. scanrate/sleep pin configuration scanrate/sleep pin connection button scan rate offset response time optimized design power consumption optimized design ground 6800 ? (1%) to ground 0 100 ? (1%) to ground 6900 ? (1%) to ground 0 200 ? (1%) to ground 7000 ? (1%) to ground 6 300 ? (1%) to ground 7100 ? (1%) to ground 12 400 ? (1%) to ground 7200 ? (1%) to ground 20 500 ? (1%) to ground 7300 ? (1%) to ground 29 600 ? (1%) to ground 7400 ? (1%) to ground 39 700 ? (1%) to ground 7500 ? (1%) to ground 49 800 ? (1%) to ground 7600 ? (1%) to ground 61 900 ? (1%) to ground 7700 ? (1%) to ground 73 1000 ? (1%) to ground 7800 ? (1%) to ground 86 1100 ? (1%) to ground 7900 ? (1%) to ground 99 1200 ? (1%) to ground 8000 ? (1%) to ground 114 1300 ? (1%) to ground 8100 ? (1%) to ground 128 1400 ? (1%) to ground 8200 ? (1%) to ground 144 1500 ? (1%) to ground 8300 ? (1%) to ground 160 1600 ? (1%) to ground 8400 ? (1%) to ground 176 1700 ? (1%) to ground 8500 ? (1%) to ground 194 1800 ? (1%) to ground 8600 ? (1%) to ground 211 1900 ? (1%) to ground 8700 ? (1%) to ground 229 2000 ? (1%) to ground 8800 ? (1%) to ground 248 2100 ? (1%) to ground 8900 ? (1%) to ground 267 2200 ? (1%) to ground 9000 ? (1%) to ground 287 2300 ? (1%) to ground 9100 ? (1%) to ground 307 2400 ? (1%) to ground 9200 ? (1%) to ground 327 2500 ? (1%) to ground 9300 ? (1%) to ground 348 2600 ? (1%) to ground 9400 ? (1%) to ground 369 2700 ? (1%) to ground 9500 ? (1%) to ground 391 2800 ? (1%) to ground 9600 ? (1%) to ground 413 2900 ? (1%) to ground 9700 ? (1%) to ground 436 3000 ? (1%) to ground 9800 ? (1%) to ground 459 3100 ? (1%) to ground 9900 ? (1%) to ground 482 3200 ? (1%) to ground 10000 ? (1%) to ground 506
cy8cmbr2010 document number: 001-74495 rev. *a page 30 of 31 ta b l e 2 3 gives the button scan rate constant according to the button count and the device optimization. for more details about this constant, refer power consumption and operating modes on page 16 . acronyms document conventions units of measure numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowerc ase 'h' (for example, '14h' or '3ah'). hexadecimal numbers may also be represented by a '0x' prefix, the c coding convention. binary numbers have an appended lowercase 'b' (for example, 01010100b' or '01000011b'). numbers not indicated by an 'h', 'b', or 0x are decimal. table 23. button scan rate constant button count button scan rate constant response time optimized design power consumption optimized design 5 25 ms 50 ms > 5 50 ms 50 ms acronym description ac alternating current ai analog input ao analog output arst auto reset dc direct current di digital input do digital output c f finger capacitance c p parasitic capacitance cs capsense fss flanking sensor suppression gpo general-purpose output i/o input/output led light-emitting diode lsb least significant bit msb most significant bit ppower pcb printed circuit board por power-on reset post power-on self test qfn quad flat no lead rf radio frequency snr signal to noise ratio symbol unit of measure c degree celsius k ? kilohm a microampere s microsecond ma milliampere mil one thousandth of an inch (1 mil = 0.0254 mm) mm millimeter ms millisecond mv millivolt na nanoampere nf nanofarad ns nanosecond ? ohm % percent pf picofarad vvolt
document number: 001-74495 rev. *a revised august 16, 2012 page 31 of 31 all products and company names mentioned in this document may be the trademarks of their respective holders. cy8cmbr2010 ? cypress semiconductor corporation, 2012. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document history page document title: cy8cmbr2010, capsense ? express? 10-button controller document number: 001-74495 revision ecn orig. of change submission date description of change ** 3561834 udyg / zine 03/30/2012 new datasheet. *a 3715110 udyg 08/16/2012 modified title. modified content in features , overview , and typical circuits section. updated ta b l e 1 , figure 1 , figure 2 , figure 9 , figure 13 , figure 14 , figure 24 , and figure 25 . minor text edits throughout the document.

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